The present invention relates generally to semiconductor devices and more particularly to methods for removing polymer residue during the fabrication of interconnect layers in semiconductor devices.
In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form electrical circuits. Interconnection of these devices within an integrated circuit is typically accomplished by forming a multi-level interconnect network in layers formed over the electrical devices, by which the device active elements are connected to one another to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching cavities such as vias and trenches. Conductive material, such as copper is then deposited into the cavities and the wafer is planarized using chemical mechanical polishing (CMP) to form an interconnect structure.
Typical interconnect structures are fabricated using single or dual damascene processes in which trenches and vias are formed (etched) in a dielectric layer. Copper is then deposited into the trenches and vias and over the insulative layer, followed by CMP planarization to leave a copper wiring pattern including the desired interconnect metal inlaid within the dielectric layer trenches. The process may be repeated to form further interconnect layers or levels by which the desired circuit interconnections are made in a multi-level interconnect network.
Etch-stop layers are often formed beneath the dielectric material layers to provide controlled stopping of the via and/or trench formation etch processes. Silicon nitride (SiN) is typically employed as an etch stop material, although recently silicon carbide (SiC) has also been used for etch-stop layers in interconnect processing. Diffusion barriers are often formed in the damascene cavities prior to deposition of copper to mitigate diffusion of copper into the dielectric material. Such barriers are typically formed using conductive compounds of transition metals such as tantalum nitride, titanium nitride, and tungsten nitride as well as the various transition metals themselves. Conductive metals, such as aluminum, copper, or the like are then used to fill the cavities after barrier layer formation, where copper is gradually replacing aluminum to improve the conductivity of the interconnect circuits.
To reduce or control RC delay times in finished semiconductor products, recent developments have focused on low dielectric constant (low-k) dielectric materials for use between the metal wiring lines, in order to reduce the capacitance therebetween and consequently to increase circuit speed. Examples of low-k dielectric materials include spin-on-glasses (SOGs), as well as organic and quasi-organic materials such as organo-silicate-glasses (OSGs), for example, having dielectric constants (k) as low as about 2.6-2.8, and ultra low-k dielectrics having dielectric constants below 2.5. OSG materials are low density silicate glasses to which alkyl groups have been added to achieve a low-k dielectric characteristic. This class of materials includes, for example, polysilsesquioxanes, such as HSQ (hydrogen silsequioxane), MSQ (methyl silsequioxane), and fluorinated silica glasses (FSGs). Totally organic, non silicaceous materials such as fluorinated polyarylene ethers, are seeing an increased usage in semiconductor processing technology because of their favorable dielectric characteristics and ease of application.
Single and dual damascene processes using OSG, FSG, or ultra low-k dielectric materials, SiC materials, and copper fill metals can thus be employed to increase speed, reduce cross talk, and reduce power consumption in modern high-speed, high-density devices. However, incorporating these newer materials into workable semiconductor fabrication processes presents additional challenges. Etch processes used to remove the etch-stop material beneath the dielectric layer or layers often leave polymer residue on the dielectric sidewalls and the bottom of the trench or via cavities, which must be cleaned or removed prior to barrier formation and filling.
This residual polymer, if left uncleaned, causes a high resistance interface between underlying conductive features and the deposited fill or barrier material, thus exacerbating RC delays. However, the cleaning process itself must not corrode or damage the underlying conductive feature to which connection is to be made. Further, the cleaning process should not change the dimensions of the cavities. Wet cleaning processes have been used in the past to remove polymers formed on oxide type dielectric sidewalls when etching through SiN type etch-stop layers. However, the recent introduction of OSG and other low-k dielectric materials in combination with SiC etch-stop materials and copper fill materials has rendered previous cleaning processes ineffective in removing polymers from OSG and other low-k dielectric sidewalls. Thus, there is a need for improved cleaning techniques by which etch-stop etch polymer residue can be cleaned or removed from interconnect structure cavities without adversely impacting device dimensions or performance.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description presented later.
The invention relates to cleaning methodologies for removing polymer from cavities such as trenches or vias during formation of interconnect structures in the manufacture of integrated circuits on a semiconductor wafer. The invention may be employed as part of a single or dual damascene interconnect process used to interconnect electrical devices formed on or in the wafer without adversely affecting dimensions thereof. In one particular application, the invention is used to remove polymer from cavities formed in OSG or low-k dielectric materials following etching of SiN or SiC type etch-stop layers to expose underlying conductive features, without significantly changing the critical dimensions of the cavities.
One aspect of the invention involves removing polymer from sidewalls in a cavity after an etch-stop etch process using a plasma comprising hydrogen or other hydrogen containing gas, and argon, helium, neon, xenon or other inert gas. When used in association with OSG type dielectrics, the cleaning plasma is nitrogen-free so as to facilitate subsequent patterning of the OSG dielectric material. In one implementation, following etch-stop etching in an etcher tool, the wafer is transferred to a plasma cleaning tool for exposure to the cleaning plasma. The cleaning plasma process removes the polymeric residue remaining from the etch-stop etch process without noticeable change in the cavity critical dimensions. The employment of hydrogen in the plasma provides a reducing chemistry, which preserves the conductivity of the exposed copper by reducing the oxygen content of portions thereof that may have oxidized. In addition, the hydrogen content in the cleaning plasma may advantageously passivate the copper against contamination from subsequent exposure to air.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.